This invention relates to methods for static timing analysis of integrated circuits, and more particularly, to methods for determining the precharge time of domino logic circuits.
A wide variety of design verification tools are required to produce a working integrated circuit from a functional specification. These tools analyze different parameters of the circuit design to ensure that the circuit will properly function after it is fabricated.
One important set of verification tools are timing analysis tools which are widely used to predict the performance of modern VLSI designs. Timing analyzers may be either static or dynamic. Dynamic timing analysis provides the most detailed and accurate information obtainable concerning the performance of the circuit. This type of timing analysis is often generated through simulation of the actual circuit by circuit simulation programs which operate at the transistor level. Examples of such circuit simulation programs are SPICE, and IBM""s ASTAP. These programs typically operate by solving matrix equations relating to the circuit parameters such as voltages, currents and resistances. Simulation approaches to performance analysis are pattern dependent, i.e., the possible paths and the delays depend on the state of the machine. Thus, the result of a dynamic timing analysis depends on the particular test pattern, or vector, applied to the circuit.
This type of simulation provides high accuracy, but long simulation times because, without knowing the best and worst case patterns beforehand, a large number of patterns must be simulated. In fact, the number of simulations which must be performed is proportional to 2n, where n is the number of inputs to the circuit under test. Thus, for circuits having a large number of inputs, dynamic timing analysis is not always practical.
Static timing analysis tools are also widely used to predict the performance of VLSI designs. Static timing analyzers are often used on very large designs for which exhaustive dynamic timing analysis is impossible. In static timing analysis, it is assumed that each signal switches independently in each machine cycle. Only the best and worst possible rising and falling times are computed for each signal in the circuit; these are often obtained in a single pass through a topologically sorted circuit. Typical static analysis methods are described in R. B. Hitchcock Sr. xe2x80x9cTiming Verification and the Timing Analysis Program.xe2x80x9d, Proc. Design Automation Conference, pp. 594-604, (1982), Jouppi, xe2x80x9cTiming Analysis and Performance Improvement of MOS VLSI Designs,xe2x80x9d IEEE Transactions on Computer-Aided Design, Vol. 6, No. 4 (1987) and Ousterhout, xe2x80x9cCrystal: A Timing Analyzer for NMOS VLSI Circuits,xe2x80x9d Proc. 3rd Cal. Tech. VLSI Conf. Computer Science Press, pp. 57-69 (1983), all hereby incorporated by reference.
FIG. 1 is an example showing a static timing analysis applied to a simple one input circuit 100, namely, an inverter. Typically, cells such as the one shown in the figure are kept in cell libraries which may be used as building blocks by engineers to construct larger and more complex integrated circuits. Typically, for each cell in the cell library, a dynamic timing analysis has already been performed, and the timing parameters of the cell are maintained as part of the cell documentation. In the example shown, cell 100 is known to have a best case delay of 30 picoseconds, and a worst case delay of 40 picoseconds, for a rising edge received at input A. Thus, if it is known that a rising edge will be received at input A at some time between 10 and 20 picoseconds measured from an initial time t0, then the best case output will be a falling edge at output B at 40 picoseconds and a worst case falling edge at output B at 60 picoseconds from time t0. Thus, the performance of the circuit is described in terms of best and worst case signal transition times, and is independent of the actual pattern received at the inputs.
Transistor-level timing analyzers decompose circuits into channel connected components, i.e., non-intersecting groups of transistors that are connected by source and drain terminals to one another and to supply and ground nets. Each channel connected component can be analyzed independently to compute the worst case delays from each input to each output for both rising and falling signals. Details of delay calculation techniques are well known to those with skill in the art, and it is sufficient to note that they commonly involve tracing paths in the channel connected component from the output net to supply and ground nets to find all possible pull-up and pull-down paths. The delay of each such path is computed independently; the worst case delay for the channel connected component is the worst of each pull-up or pull-down path delay.
Although this approach works well for many logic circuits, it tends to underestimate the precharge times for domino circuits with unclocked evaluation paths because the pull-up path delay is dependent on signals supplied to the unclocked evaluation path. Underestimating the precharge time has a snow-balling effect that could lead to serious underestimation of the total power dissipation. Accordingly, it is an object of the present invention to overcome the above described problems and to provide further improvements and advantages which will become apparent in view of the following disclosure.
One aspect of the invention relates to a method for transistor-level calculation of the precharge time of a domino logic circuit having a plurality of cascaded stages, at least one stage having an unclocked evaluation path. In one embodiment, the method comprises decomposing the at least one stage into at least one channel connected component; simulating the channel connected component to determine the pull-up time of the channel connected component relative to a transition of a clock signal; determining the pull-up times of the stages excluding the at least one stage; and summing the pull-up time of the channel connected component with the pull-up times of the stages excluding the at least one stage to determine the precharge time of the domino logic circuit.
Another aspect of the invention relates to a method for determining the precharge time of a domino logic circuit having a first stage with a clocked evaluation path and a plurality of subsequent stages with unclocked evaluation paths, the first stage and the plurality of subsequent stages being responsive to a clock signal. In one embodiment, the method comprises the steps of decomposing the individual stage into a channel connected component, and simulating the channel connected component to determine the pull-up time of the channel connected component relative to a transition of a clock signal, for individual stages with unclocked evaluation paths; and summing the pull-up times of the individual stages to determine the precharge time of the domino logic circuit.